The present invention relates to a semiconductor device, and more particularly, to a semiconductor device for suppressing power supply resonance and for suppressing fluctuation in a power supply voltage.
Normally, an inductance component parasitizes the power supply wires in a semiconductor chip. A capacitor is arranged between a high potential power supply wire and a low potential power supply wire in the chip to stabilize the power supply voltage. When a resonance frequency based on the inductance component and the capacitor coincides with the frequency of noise propagating in the high potential power supply wire or the low potential power supply wire in the semiconductor device, power supply resonance occurs and causes large fluctuations in the power supply voltage. Therefore, power supply resonance caused by noise must be prevented.
FIG. 1 is a schematic circuit block diagram of a conventional semiconductor device (chip 1). Power supply voltage is supplied from an external power supply 2 to power supply terminals t1 and t2 of the chip 1 via external wires 3a and 3b. The power supply voltage is then supplied to a signal processor 5 via internal wires 4a and 4b of the chip 1.
The external wires 3a and 3b include inductances L1 and L2 and resistors R1 and R2, respectively. The inductances L1 and L2 and the resistors R1 and R2 are actually distributed constants but are illustrated as concentrated constants in FIG. 1 for the sake of convenience. A capacitor C1 having a capacitance value of several μF to several tens of μF is connected between the output terminals of the external power supply 2 to stabilize the power supply voltage.
The internal wires 4a and 4b include inductances L3 and L4 and resistors R3 and R4, respectively. The inductances L3 and L4 and the resistors R3 and R4 are actually distributed constants but are illustrated as concentrated constants in FIG. 1. A capacitor C2 is connected between the internal wires 4a and 4b to stabilize the power supply voltage. Most of the components of the inductances L3 and L4 parasitize an interposer and bonding wire of the IC package.
With the above chip 1, when the resonance frequency of the inductances L3 and L4 and the capacitor C2 coincide with the frequency of internal noise N1 propagating from the signal processor 5 to the internal wire 4a (or 4b), power supply resonance occurs and the power supply voltage fluctuates.
Thus, the capacitance value of the capacitor C2 is set so that the resonance frequency of the inductances L3 and L4 and the capacitor C2 does not coincide with the frequency of the internal noise N1. The capacitor C2 attenuates the high frequency noise N1 output from the signal processor 5.
External noise N2 may be applied to the power supply terminals t1 and t2 via the external wires 3a and 3b. Power supply resonance also occurs and fluctuates the power supply voltage when the frequency of the noise N2 coincides with the resonance frequency of the inductances L3 and L4 of the internal wires 4a and 4b and the capacitor C2.
The connection of a capacitor between the internal wires 4a and 4b near the power supply terminals t1 and t2 in order to attenuate high frequency external noise N2 has thus been proposed.
However, it is difficult to arrange the capacitor near the power supply terminals t1 and t2 in a highly integrated chip 1. Thus, the capacitor is arranged between the signal processor 5 and the power supply terminals t1 and t2 to absorb the external noise N2 between the internal wires 4a and 4b. 
The frequency of the external noise N2 is determined in a state in which the chip 1 is mounted on a circuit board (e.g., printed circuit board). Thus, the frequency of the external noise N2 cannot be specified during the design stage of the chip 1. If power supply resonance occurs after the mounting of the chip 1, the chip 1 must be re-designed to suppress power supply resonance.
Japanese Laid-Open Patent Publication No. 2002-158448 discloses a multi-layer wiring substrate for reducing EMI noise by connecting a plurality of incorporated capacitors, which correspond to different resonance frequencies, in parallel. The capacitance value of each incorporated capacitor is controlled so that an anti-resonance frequency of each incorporated capacitor does not coincide with the frequency of a high frequency component contained in an electric signal.
Japanese Laid-Open Patent Publication No. 2002-190640 (see FIG. 1b) discloses a laser oscillator power supply device provided with a resonance switch for forming a resonance circuit in accordance with the operation of the switch.
Japanese Laid-Open Patent Publication No. 2001-175702 discloses a circuit designing method for reducing power supply noise by arranging a bypass capacitor having an optimum capacitance value at an optimum position and adjusting the resonance frequency.
Japanese Laid-Open Patent Publication No. 7-202072 discloses a semiconductor device for suppressing the power supply noise in a wide frequency band by forming a plurality of capacitors having different capacitance values in a package and setting a plurality of resonance frequencies with a bypass capacitor and a conductor inductance.
Japanese Laid-Open Patent Publication No. 2002-136103 discloses a power supply system for reducing power consumption by arranging a plurality of capacitors between an output terminal of a voltage power supply conversion circuit and ground. A capacitor having a large capacity is connected in a continuous operation mode for continuously outputting power supply voltage and disconnected in an intermittent operation mode for intermittently outputting the power supply voltage.